Dielectric resonator oscillators (DROs) are very popular devices in the radio frequency (RF) or microwave electronic field. These oscillators are typically employed in communication systems, radar systems, navigation systems and other signal receiving and/or transmitting systems. Their popularity has been attributed to their high-Q, low loss, and conveniently sized devices for various applications in the RF and microwave fields. For the purpose of this application, the terms "radio frequency", "RF" and "microwave" are interchangeable, and are used to refer to the field of electronics that involve signal processing of electromagnetic energy cycling at a frequency range of about 800 MHz to about 300 GHz.
Although DROs provide substantial advantages over other types of oscillator designs, improving their performance and characteristics is an ongoing process. For instance, some ongoing developments include reducing the size of the DROs, increasing its efficiency, improving its manufacturing and reliability, reducing its phase noise, and improving its temperature stability. Of particular interest to this invention is the latter three objectives.
Manufacturers of DROs are concerned with improving the manufacturing and reliability of their products. The design of DROs presents a particular problem in that DROs typically perform well only for an RF energy or signal cycling at a discreet frequency or within a narrow frequency range. In other words, they generally meet their specified performance only for a very narrow frequency range. It follows then that if a DRO manufacturer wants to produce a line of DROs with different discreet output frequencies covering a wide frequency range, each DRO must be custom tailored for each of the frequencies. This custom tailoring of DROs leads to increased engineering time, manufacturing time, cost, inventory and logistics, and a reduction in the reliability of the DROs.
To illustrate the manufacturing and reliability problem of customizing DROs, consider the typical prior art series feedback or reflective type DRO 10 shown in FIG. 1. The DRO 10 consists of a dielectric resonator (DR) 12, field effect transistor (FET) 14, a DR-coupling or input resonator transmission line 16, output and source impedance matching circuits 18 and 20, direct current (DC) biasing circuits 22 and 24 for the drain and source of the FET, and a FET gate return resistor R3.
In the prior art, the DRO 10 is typically designed for efficiently and optimally producing an RF energy or signal cycling at one specific frequency, or within a very narrow frequency range. For example, the DRO 10 is specifically designed to produce an RF energy or signal cycling at a frequency f.sub.0. In order for the DRO 10 to optimally perform, each of the elements of the DRO is tailored designed to optimally operate at such frequency f.sub.0. For instance, the dielectric resonator 12 is chosen such that its lowest resonating frequency is slightly below the frequency f.sub.0. Similarly, the output and source impedance matching circuits 18 and 20 are designed to provide the optimal impedance matching at frequency f.sub.0. Also, the drain and source DC biasing circuits 22 and 24 are designed so that they optimally block an RF energy or signal cycling at the operating frequency of the DRO f.sub.0.
To further illustrate the need for optimally designing each of the elements of the DRO 10 for its operating frequency f.sub.0, consider for example the drain and source DC biasing circuits 22 and 24. The object of these circuits is to transmit DC power to the FET 14 without affecting the RF energy produced by the DRO 10. To accomplish this objective, the source and drain DC biasing circuits 22 and 24 include respective high impedance transmission lines 26 and 28, each having one end (RF end) connected to an RF-carrying portion of the DRO 10, and another end (DC end) being RF shunted to ground by a bypass capacitor, such as capacitors C1 and C2.
In order for the DC biasing circuits to optimally not affect the RF energy or signal produced by the DRO 10, the length of the high impedance transmission lines 26 and 28 are designed to have a length of a quarter wavelength of an RF energy cycling at the operating frequency of the DRO f.sub.0. In addition, the bypass capacitors C1 and C2 are designed to produce an impedance to ground of less than one to two Ohms at the frequency f.sub.0. The biasing circuits 22 and 24 typically include resistors R1 and R2 for setting the proper bias voltage for the FET 14. Any deviation of the length of the high impedance transmission lines 26 and 28 from a quarter wavelength length at the operating frequency f.sub.0 of the DRO 10 will cause degradation in the performance of the DRO, such as a degradation in the phase noise performance of the device.
From the discussion above, it can be seen that in the prior art DRO 10, the elements of the DRO 10 are tailored designed for optimally operating at the specific operating frequency f.sub.0 of the DRO. This presents a problem for manufactures of DROs that need to produce a line of DROs operating at a plurality of different discreet frequencies covering a wide frequency range. In other words, because each type of DROs must be custom designed, it leads to increased engineering time, manufacturing time, cost, inventory and logistics, and a reduction in the reliability of the DROs. Thus, there is a need for a universal DRO design that can be easily modified to optimally operate at a plurality of different discreet frequencies covering a wide frequency range.
Another concern in the design of DROs is the phase noise performance of the device. Reduction in phase noise is desired since high phase noise may affect the performance of systems employing DROs. For instance, DROs often produce an RF carrier that is to be modulated with a baseband signal. If the frequency response of the baseband signal include a relatively low frequency response, its frequency components lie near the RF carrier. If the RF carrier has poor phase noise characteristics, then it will interfere with the modulated baseband signal. Thus, it is desired to reduce phase noise as much as possible in DROs to avoid this interference problem.
Referring again to FIG. 1, one particular element of the prior art DRO 10, namely the FET gate return resistor R3, can cause significant degradation in the phase noise performance of the DRO. The gate return resistor R3 is typically connected in a series feedback or reflective type DRO at the end of the DR-coupling or input resonator transmission line 16. The purpose of the gate return resistor R3 is to provide a path to ground for positive charges that accumulate on the gate of the FET 14 during its operation.
More specifically, during the operation of the DRO 10, a large signal amplitude is generated at the gate input of the FET 14. As the large signal amplitude varies over the positive half of the sinusoid wave, a small amount of positive charges pass through the Schottky diode junction of the gate. These charges interfere with operation of the DRO, and therefore, need to be removed. Thus, the FET gate resistor R3 provides a path to ground to eliminate such unwanted charges. In order to eliminate any unwanted RF reflections off the FET gate resistor R3, this resistor is designed to match the characteristic impedance of the DR-coupling or resonator transmission line 16, which is typically 50 Ohms.
Although the problem of the unwanted positive charges at the input of the DRO 10 is substantially reduced by the FET gate resistor R3, this resistor has an adverse effect of degrading the phase noise performance of the DRO. The reasons for this is that the resistance value of the resistor R3 is relatively low, e.g. 50 Ohms, and it is not properly RF isolated from the DRO circuitry, i.e., it is directly connected to the end of the DR-coupling or resonator transmission line 16. As a result, the resistor affects the RF energy propagating via that DR-coupling or resonator transmission line 16, and consequently, adversely affects the phase noise of the DRO. Accordingly, there is a need to provide a FET gate return resistor that provides a path to ground for the unwanted positive charges emanating from the FET 14, without significantly degrading the phase noise performance of the DRO.
Yet another concern in the design of DROs is the temperature stability of the device. Although DROs have superior performance when it comes to phase noise and efficiency, DROs are susceptible to environment temperature changes if they are not properly designed. Therefore, a great deal of engineering time is spent in designing temperature-compensating elements and/or techniques for DROs.
For instance, in FIG. 2, a prior art temperature-compensating DRO circuit 30 is shown. The circuit 30 includes a DRO, such as like the prior art DRO 10 of FIG. 1, coupled to a phase lock loop (PLL) circuit 32. The PLL circuit 32 includes a crystal oscillator 34, a sampling phase detector 36 and a loop filter 38. As it is conventionally known, the crystal oscillator 34 produces a highly temperature-stable sinusoidal signal with typically a much lower frequency f.sub.x than the frequency f.sub.0 of the DRO output. This sinusoidal signals coupled to a first input of the sampling phase detector 36, whereas the output sinusoidal signal of the DRO 10 is coupled to a second input of the sampling phase detector 36 by way of a directional coupler 40. The sampling phase detector 36 produces a phase error signal which is coupled to a frequency-responsive component (not shown), such as a varactor, of the DRO 10 by way of a loop filter 38.
Since the output of the crystal oscillator 34 is highly temperature stable, the output of the DRO 10 is also highly stable since the PLL circuit causes the stability DRO output frequency f.sub.0 to track the stability of the frequency f.sub.x of the crystal oscillator 34. Hence, with the PLL circuit 32, the DRO 10 is temperature stable, or as good as the temperature stability of the crystal oscillator 34.
However, this temperature stability does not come without a price. For instance, the temperature compensated DRO circuit includes additional components, such as the crystal oscillator 34, sampling phase detector 36, loop filter 38, varactor (not shown) and directional coupler 40. These additional elements add to the costs of the DRO, increases the engineering and manufacturing time, increases inventory, complicates logistics, and reduces the reliability of the DRO circuit. Thus, there is a need for a temperature-compensated DRO that does not require such additional elements. In addition, there is a further need to provide such temperature compensation in a manner that applies to a plurality of operating frequencies so that the DROs need not be custom made.